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19-6496; rev 0; 10/12 ordering information appears at end of data sheet. for related parts and recommended products to use with this part, refer to www.maximintegrated.co m / MAX14920.related . functional diagram appears at end of data sheet. general description the MAX14920/max14921 battery measurement analog front-end devices accurately sample cell voltages and provide level shifting for primary/secondary battery packs up to 16 cells/+65v (max). the MAX14920 monitors up to 12 cells, while the max14921 monitors up to 16 cells. both devices simultaneously sample all cell voltages, allowing accurate state-of-charge and source-resistance determination. all cell voltages are level shifted to ground reference with unity gain, simplifying external adc data conversion. the devices have a low-noise, low-offset amplifier that buffers differential voltages of up to +5v, allowing moni - toring of all common lithium-ion (li+) cell technologies. the resulting cell voltage error is q 0.5mv. the devices high accuracy make them ideal for monitoring cell chemistries with very flat discharge curves, such as lithium-metal phosphate. passive-cell balancing is supported by external fet drivers. integrated diagnostics in the devices allow open-wire detection and undervoltage/overvoltage alarms. the devices are controlled by a daisy-chainable spi interface. the MAX14920 is available in a 64-pin (10mm x 10mm) tqfp package with an exposed pad. the max14921 is available in an 80-pin (12mm x 12mm) tqfp package. both devices are specified over the -40c to +85c extended temperature range. applications industrial battery backup systems telecom battery backup systems energy storage packs e-transportation energy packs benefits and features s high accuracy ? 0.5mv (max) cell voltage ? simultaneous cell voltage sampling ? self-calibration s integrated diagnostics ? open-wire and short fault detection ? undervoltage/overvoltage warning ? thermal shutdown s high flexibility ? spi interface ? 12-cell and 16-cell versions ? +6v minimum (3 cells) operation ? +0.5v to +4.5v cell voltage range ? integrated cell-balancing fet drivers ? integrated 5v ldo s low power ? 1a shutdown mode ? 1a /10a cell current draw MAX14920/max14921 high-accuracy 12-/16-cell measurement afes evaluation kit available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maximintegrated.com. http://www..net/ datasheet pdf - http://www..net/
2 (all voltages referenced to agnd.) v p to agnd .......................................................... -0.3v to +70v ldoin to agnd ............................... (v a - 0.3v) to (v p + 0.3v) v a to agnd ............................................................ -0.3v to +6v cv0, dgnd to agnd .......................................... -0.3v to +0.3v sclk, sdi, cs , en .................................................. -0.3v to +6v sdo, sampl ............................................... -0.3v to (v l + 0.3v) cv1 to agnd .......................................................... -0.3v to +6v cv2Ccv12 to agnd .............. (v cv (n* - 1) - 0.3v) to (v p + 0.3v) ct1Cct12 to agnd .................... -0.3v to (v cv1 Cv cv12 + 0.3v) cb2Ccb12 to agnd ....................... -0.3v to (v cv(n* - 1) + 0.3v) cv2Ccv16 to agnd (max14921 only) .............. (v cv(m** - 1) - 0.3v) to (v p + 0.3v) ct1Cct16 to agnd (max14921 only) ...................... -0.3v to (v cv1C v cv16 + 0.3v) cb2Ccb16 to agnd (max14921 only) ....................... -0.3v to (v cv(m** - 1) + 0.3v) ba1 to agnd ......................................... -0.3v to (v cv1 + 0.3v) ba2Cba12 to agnd ........ (v cv(n* - 1) - 0.3v) to min((v cvn* + 0.3v) or +6v) ba2Cba16 to agnd (max14921 only) ........................... (v cv(m** - 1) - 0.3v) to min ((v cvm** + 0.3v) or +6v) aout, t1, t2, t3 to agnd ......................... -0.3v to (v a + 0.3v) continuous power dissipation (t a = +70 c) 64-pin tqfp-ep (derate 31.3mw/c above +70c)...2508mw 80-pin tqfp (derate 23.3mw/ c above +70 c) ........ 1860mw operating temperature range .......................... -40 n c to +85 c maximum junction temperature ..................................... +150 c storage temperature range ............................ -65 n c to +150 c lead temperature (soldering, 10s) ................................ +300 c soldering temperature (reflow) ...................................... +260 c * n = 2C12 ** m = 2C16 absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc electrical characteristics (v p = +65v, dgnd = agnd, v l = v en = +3.3v, v a = +5v, c sample = 1 f f, t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c.) (note 2) junction-to-ambient thermal resistance ( q ja ) 64-pin tqfp-ep..........................................................31.9c/w 80-pin tqfp .................................................................. 43 c/w junction-to-case thermal resistance ( q jc ) 64-pin tqfp-ep...............................................................1c/w 80-pin tqfp .................................................................... 8 c/w note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . package thermal characteristics (note 1) parameter symbol conditions min typ max units power supplies v p supply voltage v p +6 +65 v v p supply current i p_off en = low or lopw = 1 1 f a i p_on en = high 65 150 ldoin supply voltage v ldoin +6 +65 v ldoin supply current i ldoin_off en = low, i a = 0a 75 125 f a i ldoin_on en = high, i a = 0a 350 500 v a analog supply voltage v a v a supply externally, v a = v ldoin +4.75 +5 +5.25 v v a analog supply current i a_off en = low, v a = v ldoin 50 75 f a i a_on en = high, v a = v ldoin 350 450 v l supply voltage v l +1.62 +5.5 v v l supply current i l all logic inputs static, held at logic-low or logic-high 2.5 5 f a maxim integrated MAX14920/max14921 high-accuracy 12-/16-cell measurement afes http://www..net/ datasheet pdf - http://www..net/
3 dc electrical characteristics (continued) (v p = +65v, dgnd = agnd, v l = v en = +3.3v, v a = +5v, c sample = 1 f f, t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c.) (note 2) parameter symbol conditions min typ max units v p uvlo uv_v pvth v p rising +6 v uvlo hysteresis uv_v physt 200 mv ldoin uvlo uv_ldoin vt v ldoin rising +5.25 +6 v v a uvlo uv_v avth v a rising +4.7 v v l uvlo uv_v lvth v l rising +1.6 v ldo output voltage v a_ldo_out 0 < i load < 10ma +4.75 +5 +5.25 v analog inputs (t1, t2, t3) input signal range v t reference to agnd 0 v a v on-resistance r ona 200 i input leakage current i t_leak t_ route to buffer amplifier -1 +1 f a t_ route to aout -1 +1 capacitor inputs (ct_) capacitor discharge current i lt_ hold phase, sampl = low -1 +1 f a analog inputs (cv_) differential input signal range for guaranteed accuracy v dn v cvn C v cvn-1 (note 3) +0.5 +4.5 v cv1 input voltage range v cv1 0 +5 v cv2Ccv12 input voltage range (MAX14920) v cvn n 2, v cvn v cvn-1 (note 3) +1.5 +65 v cv2Ccv16 input voltage range (max14921) v cvm m 2, v cvm v cvm-1 (note 3) +1.5 +65 v input leakage current i ls_ during sampling phase -1 +1 f a i lh_ during holding phase -1 +10 i lc_ during calibration -1 +10 i ld_ during diagnostics, diag = 1 10 balancing input current i lb_ ba_ active, v cvn - v cvn-1 = +4.5v (note 3) 6.5 12 ma sample switch on-resistance r sample v cvn > +2v, i sink = 2ma (note 3) 80 150 i v cvn > +1.5v, i sink = 1ma (note 3) 90 r swcal v cvn > +2v, i sink = 2ma (note 3) 800 16,000 cell undervoltage threshold uv_v cvth an undervoltage sets the associated spi cn bit +1.4 +1.5 +1.6 v cell overvoltage threshold ov_v cvth an overvoltage sets the associated spi cn bit v a v maxim integrated MAX14920/max14921 high-accuracy 12-/16-cell measurement afes http://www..net/ datasheet pdf - http://www..net/
4 dc electrical characteristics (continued) (v p = +65v, dgnd = agnd, v l = v en = +3.3v, v a = +5v, c sample = 1 f f, t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c.) (note 2) parameter symbol conditions min typ max units analog output (aout) output signal range v aout reference to agnd +0.3 v a - 0.3 v amplifier offset voltage v offset v aout = +3.3v, after self-calibration (note 5) q 50 q 100 f v temperature offset drift if not recalibrated q 1.5 f v/c gain a_v gain = v aout/ v d 1 v/v output error v o_err (note 4) -0.5 +0.5 mv amplifier gain error v gain_err r out = 100k i , v d = 2v to 4.5v (note 6) -0.2 +0.2 mv v p monitor voltage v pmon [sc0, sc1, sc2, sc3] = [0, 0, 1, 1] MAX14920 v p /12 v max14921 v p /16 v p monitor accuracy v pmona [sc0, sc1, sc2, sc3] = [0, 0, 1, 1] -0.25 0 +2.5 % charge-balance drivers (ba_) output low v bal i ba_ = 1ma, v cv(n) - v cv(n - 1) = +3.3v (note 3) v cv(n - 1) v cv(n - 1) + 0.9 v output high v bah i ba_ = -1ma, v cv(n) - v cv(n - 1) = +3.3v (note 3) v cv(n) - 1.5 v cv(n) v pulldown resistance r pdwn 0.65 0.9 k i logic output (sdo) output low voltage v ol i sink = 10ma +0.9 v output high voltage v oh i source = 0.5ma v l - 0.25 v output leakage current i l v cs = v l -1 +1 f a logic inputs (sdi, sclk, en, sampl) input low voltage v il v l < +2.3v 0.2 x v l v +2.3v < v l < +5.5v 0.3 x v l input high voltage v hl v l < +2.3v 0.8 x v l v +2.3v < v l < +5.5v 0.7 x v l input leakage current i l -1 +1 f a dynamic characteristics aout settling time t set measured between channels with +4v signal change. settling to q 1mv accuracy, c load = 100pf (figure 1) 5 f s sampling time t sampl c sample = 1 f f 4 ms c sample = 1 f f, error calibration 40 holding delay time t hd delay from smplb set to 1 or sampl falling edge to holding of all cell voltages 0.5 f s maxim integrated MAX14920/max14921 high-accuracy 12-/16-cell measurement afes http://www..net/ datasheet pdf - http://www..net/
5 dc electrical characteristics (continued) (v p = +65v, dgnd = agnd, v l = v en = +3.3v, v a = +5v, c sample = 1 f f, t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c.) (note 2) note 2: all devices are 100% production tested at t a = +25c. limits over the operating temperature range are guaranteed by design. note 3: where n = 1C12 (MAX14920) and n = 1C16 (max14921). note 4: output error v o_err is the difference between the input cell difference voltage (v d = v cv(n) - v cv(n - 1) ) and the output voltage v aout . where n = 1C12 (MAX14920) and n = 1C16 (max14921). output error depends on buffer ampli - fier errors and parasitic capacitance charge injection error. since parasitic capacitance error is pcb dependent, output error is guaranteed by design for a sampling capacitor of 1 f f and parasitic capacitance less than 2.5pf on ctn (see the measurement accuracy section for a detailed explanation). note 5: buffer amplifier self-calibrates its offset at power-up and every time it is requested. due to possible thermal drift after power-up phase, it is suggested to run self-calibration on a regular basis to get best performance (see the buffer amplifier offset calibration section for a detailed explanation). note 6: amplifier error is the sum of all errors including amplifier offset and gain error. parameter symbol conditions min typ max units level-shifting delay time t ls_delay delay from smplb set to 1 or sampl falling edge to shifting of all cell voltages to ground and available for reading 25 50 f s aout voltage-droop time t droop droop to -1mv (figure 2) 1 ms t_ settling time t ts measured between t_ input selection and aout settling to +1mv accuracy, c load = 100pf, sc2 = 1 5 f s t_ turn-on delay time t td 0.2 f s v p settling time t vps measured between v p /12 (MAX14920), v p /16 (max14921) input selection and aout, settling to 2.5%, c load = 100pf, sc3 = 1 25 60 f s self-calibration time 8 ms thermal detection thermal shutdown +140 c thermal-shutdown hysteresis 15 c spi timings (figure 3) sdi to sclk setup t ds 50 ns sdi to sclk hold t dh 12 ns sclk to sdo valid t do 100 ns cs fall to sdo enable t dv 100 ns cs rise to sdo disable t tr 80 ns cs pulse width t csw 50 ns cs fall to sclk rise setup t css 100 ns cs rise to sclk rise hold t csh 0 ns sclk high pulse width t ch 65 ns sclk low pulse width t cl 65 ns sclk period t cp 208 ns maxim integrated MAX14920/max14921 high-accuracy 12-/16-cell measurement afes http://www..net/ datasheet pdf - http://www..net/
6 timing diagrams figure 1. aout delay from spi select figure 2. aout voltage-droop time figure 3. spi timing cs sclk sdi aout c1 c2 c3 c4 c16 t1 t2 t3 ot 0v *n = 1?12 (MAX14920) and n = 1?16 (max14921 ) t set sdi sdo sclk cs t css t ds t dh t do t dv t tr t ch t csh t cl *n = 1?12 (MAX14920) and n = 1?16 (max14921 ) sampl aout 1mv v cvn* t droop t sampl maxim integrated MAX14920/max14921 high-accuracy 12-/16-cell measurement afes http://www..net/ datasheet pdf - http://www..net/
7 typical operating characteristics (v cvn - v cv(n - 1) = +3.3v (where n = 1C12 (MAX14920) and n = 1C16 (max14921)), t a = +25c, unless otherwise noted.) i p vs. v p MAX14920 toc01 v p (v) i p (a) 45 25 10 20 30 40 50 60 0 56 5 sample mode ldo disabled t a = +85c t a = +25c t a = -40c t a (c) i p (a) 60 35 10 -15 10 20 30 40 50 60 0 -40 85 i p vs. temperature MAX14920 toc02 sample mode ldo disabled v p = 6v v p = 24v v p = 65v ldo output voltage change vs. load current MAX14920 toc03 i out (ma) change in output voltage (%) 8 6 4 2 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 01 0 v p = 10v voltage error vs. cell voltage MAX14920 toc04 cell voltage (v) error (mv) 3.5 2.5 1.5 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 -0.4 0.5 4.5 v cvn-1 = 40v t sample = 4ms v cvn-1 = 20v v cvn-1 = 60v v cvn-1 = 0v t a (c) v aout settling time (s) 60 35 10 -15 1 2 3 4 5 6 0 -40 85 v aout settling time vs. temperature MAX14920 toc05 t sample = 4ms v cvn - v cvn-1 = 1.5v v p = 24v settle to 1mv v aout droop time vs. temperature MAX14920 toc06 t a (c) v aout droop time (ms) 60 35 10 -15 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 -40 85 t sample = 4ms v cvn - v cvn-1 = 1.5v v p = 24v t_ on-resistance vs. v t_ MAX14920 toc07 v t_ (v) r on (i) 4 3 2 1 20 40 60 80 100 120 140 160 180 200 0 05 i t_ = 0.1ma v ban - v cvn-1 vs. i ban MAX14920 toc08 i ban (ma) v ban - v cvn-1 (v) 4 3 2 1 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 05 v cvn - v cvn-1 = 3.3v v oh v l supply current vs. temperature MAX14920 toc09 t a (c) v l supply current (a) 60 35 10 -15 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 -40 85 v l = 5v sampl = v l v l = 3.3v v l = 1.8v maxim integrated MAX14920/max14921 high-accuracy 12-/16-cell measurement afes http://www..net/ datasheet pdf - http://www..net/
8 pin configurations 58 59 60 61 62 54 55 56 57 63 38 39 40 41 42 43 44 45 46 47 cv1 sdo cv4 64 tqfp-ep (10mm x 10mm) top view cb5 ct5 ba5 cv5 cb6 ct6 ba6 cv6 cb7 52 53 49 50 51 ct7 ba7 cv7 cb8 ct8 sdi v l sampl t3 dgnd t1 t2 agnd aout ldoin v a cv12 v p ba12 cv8 cb9 ct9 ba9 cv9 cb10 ct10 ba10 cv10 cb11 33 34 35 36 37 ct11 ba11 cv11 cb12 ct12 + cb2 ct2 ba2 cv2 cb3 cs *ep *connect ep to gnd en cv0 ct1 ba1 ct3 ba3 cv3 cb4 48 ba8 ct4 64 ba4 sclk 23 22 21 20 19 27 26 25 24 18 29 28 32 31 30 17 11 10 9 8 7 6 5 4 3 21 6 15 14 13 12 1 MAX14920 maxim integrated MAX14920/max14921 high-accuracy 12-/16-cell measurement afes http://www..net/ datasheet pdf - http://www..net/
9 pin configurations (continued) top view sdo 80 tqfp (12mm x 12mm) sdi v l sampl t3 dgnd t1 t2 agnd aout ldoin v a cv16 v p ba16 cv11 cb12 ct12 ba12 cv12 cb13 ct13 ba13 cv13 cb14 ct14 ba14 cv14 cb15 ct15 + ba11 sclk 27 26 25 24 23 31 30 29 28 22 33 32 36 35 34 21 cv10 cb11 ct11 ba10 37 40 39 38 74 75 76 77 78 70 71 72 73 79 68 69 65 66 67 80 64 61 62 63 11 10 9 8 7 6 5 4 3 21 6 15 14 13 ct16 cv15 cb16 ba15 20 19 18 17 12 1 50 51 52 53 54 55 56 57 58 59 45 46 47 48 41 42 43 44 49 60 max14921 cb6 cv5 ba6 ct6 cb7 cv6 ba7 ct7 cb8 cv7 ba8 ct8 cb9 cv8 ct9 ba5 ba9 cb10 cv9 ct10 cb4 cv3 ba3 ct3 cb3 cv2 ba2 ct2 cb2 cv1 ba1 ct1 cv0 en cs ct4 cb5 cv4 ba4 ct5 maxim integrated MAX14920/max14921 high-accuracy 12-/16-cell measurement afes http://www..net/ datasheet pdf - http://www..net/
10 pin description pin name function MAX14920 (64 tqfp-ep) max14921 (80 tqfp) 1 1 sclk spi clock input 2 2 sdi spi data line input 3 3 sdo spi data line output 4 4 sampl sample control input. voltages at cv_ inputs are tracked when sampl is logic- high. when sampl transitions from high to low, the differential voltages on cv_ are held internally and made ready for readout at the aout output. 5 5 v l logic supply input. bypass v l to dgnd with a 0.1 f f capacitor as close as possible to the device. 6 6 dgnd digital ground 7 7 t3 single-ended voltage input. t3 can be connected to a temperature sensor or other analog voltage. 8 8 t2 single-ended voltage input. t2 can be connected to a temperature sensor or other analog voltage. 9 9 t1 single-ended voltage input. t1 can be connected to a temperature sensor or other analog voltage. 10 10 aout buffered amplifier output 11 11 agnd analog ground. agnd is a low-noise ground. connect cv0 to agnd. connect dgnd to agnd. 12 12 v a +5v ldo output. bypass v a to agnd with a 1 f f capacitor as close as possible to the device. 13 13 ldoin +5v ldo power supply. connect ldoin to v p to enable the ldo. connect ldoin to v a to disable the ldo and use an external +5v supply. 14 14 v p power supply. connect to the highest voltage of the battery cell stack. bypass v p to agnd with a 0.1 f f capacitor as close as possible to the device. 15 31 cv12 cell voltage input 12. connect cv12 to cell anode/cathode. connect cv12 to the highest voltage of the battery cell stack if not used. 16 32 ba12 cell-balancing gate driver output 12. connect ba12 to the gate of the external n-channel fet. leave ba12 unconnected if not used. 17 33 ct12 sampling capacitor 12 high terminal. ct12 internally connects to cv12 when sampl is logic-high. connect a 1 f f capacitor between ct12 and cb12. leave ct12 unconnected if not used. 18 34 cb12 sampling capacitor 12 low terminal. cb12 internally connects to cv11 when sampl is logic-high. connect a 1 f f capacitor between ct12 and cb12. leave cb12 unconnected if not used. 19 35 cv11 cell voltage input 11. connect cv11 to cell anode/cathode. connect cv12 to the highest voltage of the battery cell stack if not used. 20 36 ba11 cell-balancing gate driver output 11. connect ba11 to the gate of the external n-channel fet. leave ba11 unconnected if not used. maxim integrated MAX14920/max14921 high-accuracy 12-/16-cell measurement afes http://www..net/ datasheet pdf - http://www..net/
11 pin description (continued) pin name function MAX14920 (64 tqfp-ep) max14921 (80 tqfp) 21 37 ct11 sampling capacitor 11 high terminal. ct11 internally connects to cv11 when sampl is logic-high. connect a 1 f f capacitor between ct11 and cb11. leave ct11 unconnected if not used. 22 38 cb11 sampling capacitor 11 low terminal. cb11 internally connects to cv10 when sampl is logic-high. connect a 1 f f capacitor between ct11 and cb11. leave cb11 unconnected if not used. 23 39 cv10 cell voltage input 10. connect cv10 to cell anode/cathode. connect cv10 to the highest voltage of the battery cell stack if not used. 24 40 ba10 cell-balancing gate driver output 10. connect ba10 to the gate of the external n-channel fet. leave ba10 unconnected if not used. 25 41 ct10 sampling capacitor 10 high terminal. ct10 internally connects to cv10 when sampl is logic-high. connect a 1 f f capacitor between ct10 and cb10. leave ct10 unconnected if not used. 26 42 cb10 sampling capacitor 10 low terminal. cb10 internally connects to cv9 when sampl is logic-high. connect a 1 f f capacitor between ct10 and cb10. leave cb10 unconnected if not used. 27 43 cv9 cell voltage input 9. connect cv9 to cell anode/cathode. connect cv9 to the highest voltage of the battery cell stack if not used. 28 44 ba9 cell-balancing gate driver output 9. connect ba9 to the gate of the external n-channel fet. leave ba9 unconnected if not used. 29 45 ct9 sampling capacitor 9 high terminal. ct9 internally connects to cv9 when sampl is logic-high. connect a 1 f f capacitor between ct9 and cb9. leave ct9 unconnected if not used. 30 46 cb9 sampling capacitor 9 low terminal. cb9 internally connects to cv8 when sampl is logic-high. connect a 1 f f capacitor between ct9 and cb9. leave cb9 unconnected if not used. 31 47 cv8 cell voltage input 8. connect cv8 to cell anode/cathode. connect cv8 to the highest voltage of the battery cell stack if not used. 32 48 ba8 cell-balancing gate driver output 8. connect ba8 to the gate of the external n-channel fet. leave ba8 unconnected if not used. 33 49 ct8 sampling capacitor 8 high terminal. ct8 internally connects to cv8 when sampl is logic-high. connect a 1 f f capacitor between ct8 and cb8. leave ct8 unconnected if not used. 34 50 cb8 sampling capacitor 8 low terminal. cb8 internally connects to cv7 when sampl is logic-high. connect a 1 f f capacitor between ct8 and cb8. leave cb8 unconnected if not used. 35 51 cv7 cell voltage input 7. connect cv7 to cell anode/cathode. connect cv7 to the highest voltage of the battery cell stack if not used. maxim integrated MAX14920/max14921 high-accuracy 12-/16-cell measurement afes http://www..net/ datasheet pdf - http://www..net/
12 pin description (continued) pin name function MAX14920 (64 tqfp-ep) max14921 (80 tqfp) 36 52 ba7 cell-balancing gate driver output 7. connect ba7 to the gate of the external n-channel fet. leave ba7 unconnected if not used. 37 53 ct7 sampling capacitor 7 high terminal. ct7 internally connects to cv7 when sampl is logic-high. connect a 1 f f capacitor between ct7 and cb7. leave ct7 unconnected if not used. 38 54 cb7 sampling capacitor 7 low terminal. cb7 internally connects to cv6 when sampl is logic-high. connect a 1 f f capacitor between ct7 and cb7. leave cb7 unconnected if not used. 39 55 cv6 cell voltage input 6. connect cv6 to cell anode/cathode. connect cv6 to the highest voltage of the battery cell stack if not used. 40 56 ba6 cell-balancing gate driver output 6. connect ba6 to the gate of the external n-channel fet. leave ba6 unconnected if not used. 41 57 ct6 sampling capacitor 6 high terminal. ct6 internally connects to cv6 when sampl is logic-high. connect a 1 f f capacitor between ct6 and cb6. leave ct6 unconnected if not used. 42 58 cb6 sampling capacitor 6 low terminal. cb6 internally connects to cv7 when sampl is logic-high. connect a 1 f f capacitor between ct6 and cb6. leave cb6 unconnected if not used. 43 59 cv5 cell voltage input 5. connect cv5 to cell anode/cathode. connect cv5 to the highest voltage of the battery cell stack if not used. 44 60 ba5 cell-balancing gate driver output 5. connect ba5 to the gate of the external n-channel fet. leave ba5 unconnected if not used. 45 61 ct5 sampling capacitor 5 high terminal. ct5 internally connects to cv5 when sampl is logic-high. connect a 1 f f capacitor between ct5 and cb5. leave ct5 unconnected if not used. 46 62 cb5 sampling capacitor 5 low terminal. cb5 internally connects to cv4 when sampl is logic-high. connect a 1 f f capacitor between ct5 and cb5. leave cb5 unconnected if not used. 47 63 cv4 cell voltage input 4. connect cv4 to cell anode/cathode. connect cv4 to the highest voltage of the battery cell stack if not used. 48 64 ba4 cell-balancing gate driver output 4. connect ba4 to the gate of the external n-channel fet. leave ba4 unconnected if not used. 49 65 ct4 sampling capacitor 4 high terminal. ct4 internally connects to cv4 when sampl is logic-high. connect a 1 f f capacitor between ct4 and cb4. leave ct4 unconnected if not used. 50 66 cb4 sampling capacitor 4 low terminal. cb4 internally connects to cv3 when sampl is logic-high. connect a 1 f f capacitor between ct4 and cb4. leave cb4 unconnected if not used. maxim integrated MAX14920/max14921 high-accuracy 12-/16-cell measurement afes http://www..net/ datasheet pdf - http://www..net/
13 pin description (continued) pin name function MAX14920 (64 tqfp-ep) max14921 (80 tqfp) 51 67 cv3 cell voltage input 3. connect cv3 to cell anode/cathode. connect cv3 to the highest voltage of the battery cell stack if not used. 52 68 ba3 cell-balancing gate driver output 3. connect ba3 to the gate of the external n-channel fet. leave ba3 unconnected if not used. 53 69 ct3 sampling capacitor 3 high terminal. ct3 internally connects to cv3 when sampl is logic-high. connect a 1 f f capacitor between ct3 and cb3. leave ct3 unconnected if not used. 54 70 cb3 sampling capacitor 3 low terminal. cb3 internally connects to cv2 when sampl is logic-high. connect a 1 f f capacitor between ct3 and cb3. leave cb3 unconnected if not used. 55 71 cv2 cell voltage input 2. connect cv2 to cell anode/cathode. connect cv2 to the highest voltage of the battery cell stack if not used. 56 72 ba2 cell-balancing gate driver output 2. connect ba2 to the gate of the external n-channel fet. leave ba2 unconnected if not used. 57 73 ct2 sampling capacitor 2 high terminal. ct2 internally connects to cv2 when sampl is logic-high. connect a 1 f f capacitor between ct2 and cb2. leave ct2 unconnected if not used. 58 74 cb2 sampling capacitor 2 low terminal. cb2 internally connects to cv1 when sampl is logic-high. connect a 1 f f capacitor between ct2 and cb2. leave cb2 unconnected if not used. 59 75 cv1 cell voltage input 1. connect cv1 to cell anode/cathode. 60 76 ba1 cell-balancing gate driver output 1. connect ba1 to the gate of the external n-channel fet. leave ba1 unconnected if not used. 61 77 ct1 sampling capacitor connection 1 high terminal. ct1 internally connects to cv1 when sampl is logic-high. connect a 1 f f capacitor between ct1 and cv0. leave ct1 unconnected if not used. 62 78 cv0 cell voltage input 0. connect cv0 to agnd. 63 79 en enable input. drive en low to put the device into shutdown mode and reset the spi registers. the +5v ldo remains active in the shutdown mode. drive en high for normal operation. 64 80 cs spi chip-select input. active low. 15 cv16 cell voltage input 16. connect cv16 to cell anode/cathode. connect cv16 to the highest voltage of the battery cell stack if not used. 16 ba16 cell-balancing gate driver output 16. connect ba16 to the gate of the external n-channel fet. leave ba16 unconnected if not used. 17 ct16 sampling capacitor connection 16 high terminal. ct16 internally connects to cv16 when sampl is logic-high. connect a1 f f capacitor between ct16 and cb16. leave ct16 unconnected if not used. maxim integrated MAX14920/max14921 high-accuracy 12-/16-cell measurement afes http://www..net/ datasheet pdf - http://www..net/
14 pin description (continued) pin name function MAX14920 (64 tqfp-ep) max14921 (80 tqfp) 18 cb16 sampling capacitor connection 16 low terminal. cb16 internally connects to cv15 when sampl is logic-high. connect a 1 f f capacitor between ct16 and cb16. leave cb16 unconnected if not used. 19 cv15 cell voltage input 15. connect cv15 to cell anode/cathode. connect cv15 to the highest voltage of the battery cell stack if not used. 20 ba15 cell-balancing gate driver output 15. connect ba15 to the gate of the external n-channel fet. leave ba15 unconnected if not used. 21 ct15 sampling capacitor connection 15 high terminal. ct15 internally connects to cv15 when sampl is logic-high. connect a 1 f f capacitor between ct15 and cb15. leave ct15 unconnected if not used. 22 cb15 sampling capacitor connection 15 low terminal. cb15 internally connects to cv14 when sampl is logic-high. connect a 1 f f capacitor between ct15 and cb15. leave cb15 unconnected if not used. 23 cv14 cell voltage input 14. connect cv14 to cell anode/cathode. connect cv14 to the highest voltage of the battery cell stack if not used. 24 ba14 cell-balancing gate driver output 14. connect ba14 to the gate of the external n-channel fet. leave ba14 unconnected if not used. 25 ct14 sampling capacitor connection 14 high terminal. ct14 internally connects to cv14 when sampl is logic-high. connect a 1 f f capacitor between ct14 and cb14. leave ct14 unconnected if not used. 26 cb14 sampling capacitor connection 14 low terminal. cb14 internally connects to cv13 when sampl is logic-high. connect a 1 f f capacitor between ct14 and cb14. leave cb14 unconnected if not used. 27 cv13 cell voltage input 13. connect cv13 to cell anode/cathode. connect cv13 to the highest voltage of the battery cell stack if not used. 28 ba13 cell-balancing gate driver output 13. connect ba13 to the gate of the external n-channel fet. leave ba13 unconnected if not used. 29 ct13 sampling capacitor connection 13 high terminal. ct13 internally connects to cv13 when sampl is logic-high. connect a 1 f f capacitor between ct13 and cb13. leave ct13 unconnected if not used. 30 cb13 sampling capacitor connection 13 low terminal. cb13 internally connects to cv12 when sampl is logic-high. connect a 1 f f capacitor between ct13 and cb13. leave cb13 unconnected if not used. ep exposed pad (MAX14920 only). connect ep to agnd. maxim integrated MAX14920/max14921 high-accuracy 12-/16-cell measurement afes http://www..net/ datasheet pdf - http://www..net/
15 detailed description the MAX14920/max14921 analog front-end devices are used in multicell battery measurement systems to moni - tor primary/secondary battery packs up to 16 cells/+65v (max). the devices perform the signal conditioning required for enabling accurate cell voltage measurement. both devices simultaneously sample all cell voltages, allowing accurate state-of-charge and source-resistance determination, even under transient load current condi - tions. the cell voltage measurements are shifted down to ground reference with unity gain, simplifying external adc data conversion. the devices enable passive cell balanc - ing through drivers that control external discharge fets. a high-accuracy, low-offset amplifier buffers differen - tial voltages up to +5v for monitoring of the common rechargeable cell technologies such as lithium-ion (li+). the resulting cell measurement errors from the devices are below q 0.5mv (max). the devices high accuracy make them ideal for monitoring cell chemistries with very flat discharge curves, such as a lithium-metal phosphate cell. diagnostics detect open-wire and short conditions, and warn about overvoltage/undervoltage. the spi interface is used for control and monitoring through a host controller. the spi interface is daisy- chainable. both devices can operate with a minimum of +6v total stack voltage (typically equating to 3 cells). voltage sampling the voltages of all cells are tracked by the sampling capacitors connected between the ctn and cbn pins (where n = 1C12 (MAX14920) and n = 1C16 (max14921)), while the smplb bit is set to 0 and the sampl input is driven high ( figure 4 ). when the smplb bit is set to 1, and the sampl input transitions low, all cell voltages are simultaneously sampled on their associated capacitors. the voltages are held by the capacitors while the smplb bit is 1, or the sampl pin is held low. when sample and holding is controlled by the sampl input, set the smplb bit to 0. when sample and hold is controlled by the smplb bit, keep the sampl input high. in sample phase selecting any cell voltage (ecs = 1), aout equals v p /12 (MAX14920) or v p /16 (max14921). resistors can be placed in series with the cv_ inputs to filter transients and/or for protection. consider the switches on-resistance of 150 i (max) when calculating the filter and settling times. in the holding phase, each capacitors voltage can be independently routed to the analog aout output under spi control. voltage readout when the smplb bit is set high, or when the sampl input is driven low, the sampling switches are opened after 0.5 f s (typ) and the cell voltages are held on the external sampling capacitors. within the time of t ls_delay < 50 f s (max), the capacitors voltages are all shifted to ground reference. then the undervoltage/overvoltage monitor - ing of all cells is valid and the cell voltage is available for sequential readout under spi control. the spi control can select the readout of any cell voltages, in any order ( figure 5 ). with the ecs bit set to 1, a selected cells voltage appears at the aout output according to the cell selection (as defined by the sc_ cell select bits). a low-leakage, low- noise, low-offset amplifier buffers the capacitor charge and provides the high-accuracy aout analog output. after a settling time of t set , from the rising edge of the cs signal, the voltage is available at aout with speci - fied accuracy. an adc can then sample and convert the aout voltage. the aout output voltage droops over time due to capacitor discharge. the droop time for 1mv of change is larger than t droop (> c sample /i ct_leak ). figure 4. voltage sampling *n = 1?12 (MAX14920) and n = 1?16 (max14921) cvn* - 1 sampl c sample smplb cvn* ctn* cbn* MAX14920 max14921 maxim integrated MAX14920/max14921 high-accuracy 12-/16-cell measurement afes http://www..net/ datasheet pdf - http://www..net/
16 figure 5. spi control cells voltage readout measurement accuracy the accuracy of cell voltage monitoring (i.e., the differ - ence of the aout voltage relative to the cell voltages) is determined by three factors: 1) held voltage droop due to leakage on the ct_ pins 2) internal buffer amplifiers voltage errors 3) capacitive level-shifting circuit error the ct_ leakage (1 f a, max) is a current that mainly comes from the cv_ pin and increases with temperature. neglecting the pcb leakage across the sampling capaci - tance, the voltage drift error is given by: = ct_leak err_leak readout sample i v xt c where: c sample is the sampling capacitance i ct_leak is the leakage current on the ct_ pin t readout is the delay between hold starts and read - out of the cell voltage for example, with 1 f f sampling capacitors and an adc conversion rate > 20khz, v err_leak is less than 1mv. cells with a higher common-mode voltage have a higher leakage. to reduce the voltage drift over time, start sequential voltage readout from the highest cell in the stack first. the buffer amplifier errors are nondeterministic in nature, and vary from chip to chip. they are also affected by temperature. the buffer amplifier offset error can be cali - brated out through an internal offset-calibration function. this calibration is automatically performed at power-up. the calibration can also be initiated under spi control. due to temperature drifts over time, it is best done on a regular basis. once the buffer amplifier offset is cali - brated out, the total error of the buffer is below 0.3mv. after power-up, if the devices do not calibrate regularly, a temperature offset drift of q 1.5 f v/ n c can occur. the level shifting is subject to deterministic errors due to charge injection by parasitic pcb-related capacitance on the ct_ pins. the charge-injected sampling error can be calculated as follows: sampl sw sample err_charge_injection par ctn t /(2r x c ) sample v c1 xv x c 1e ? = ?? ?? ? ?? where: c par is the parasitic capacitance of the ctn pin, where n = 1C12 (MAX14920) and n = 1C16 (max14921) c sample is the sampling capacitor r sw is the sampling switch resistance v ctn is the voltage of the ctn pin with respect to agnd, where n = 1C12 (MAX14920) and n = 1C16 (max14921) t sampl is the sampling time sample phase hold phase convert cell m convert cell n select cell n convert cell b select cell c t sampl t set t set t set t d_h t d_ls settling level shift hold delay = voltage ready = spi activity = adc conversion convert cell a select cell b select cell a maxim integrated MAX14920/max14921 high-accuracy 12-/16-cell measurement afes http://www..net/ datasheet pdf - http://www..net/
17 figure 6. charge injection sampling error voltage for 1pf parasitic capacitance figure 6 shows the charge-injected sampling error for 1pf of parasitic capacitance in worst-case conditions for a 1 f f sampling capacitor. minimizing the parasitic capacitance on the ct_ pins to a few picofarads, with a sampling capacitor of 1 f f, is enough to achieve output error below 1mv target. this error can be further reduced by increasing the sampling capacitor value and consequently increasing the sampling time. alternatively, if a sampling capacitor lower than 1 f f or a parasitic capacitance of more than 15pf are present, these errors can be calibrated out to achieve a < 1mv accuracy level through a calibration procedure for each cell. these per-cell errors are simply subtracted from every cell volt - age measurement (see the parasitic capacitance charge injection error calibration section). parasitic capacitance charge injection error calibration this calibration is performed with all cells connected to the cv_ terminals. setting the [ecs, sc0, sc1, sc2, sc3] bits to [0, 0, 0, 0, 0] configure the devices for para - sitic capacitance charge-injection error calibration. during the sampling phase, every capacitors termi - nals are shorted by an internal calibration sampling switch (r swcal = 800 i typ), so that only the parasitic capacitance is charged to the cells common-mode volt - age v ctn , where n = 1C12 (MAX14920) and n = 1C16 (max14921). the subsequent cell voltage readout sequence then shows the value of v err_charge_injection for each of the 12/16 cells at aout, multiplied by 128. if v err__charge_injection is large enough to affect the required 1mv accuracy, this calibration method provides a measurement of the parasitic capacitance on each ct_ pin so the microcontroller can use this to correct v err_injection in its readings. different correction algorithms are possible for the microcontroller using the calibration readout voltages. a simple way to correct cell voltages is to store the adc data of each cell obtained during calibration (i.e., error values), divided by 128, and subtract these from the subsequently measured cell voltages. buffer amplifier offset calibration on power-up, the devices automatically go through a self-calibration phase to minimize the internal buffers offset voltage. in addition, the offset voltage can be cali - brated out at any time under host control. offset calibra - tion is configurable by setting the [ecs, sc0, sc1, sc2, sc3] bits to [0, 1, 0, 0] and is initiated on the low to high cs transition in sampling phase. this offset-calibration procedure takes 8ms to complete. the aout output is high impedance during this period. no regular cell volt - age measurement can be taken during this time period. however, the spi operates normally when communicat - ing with other devices (e.g., in daisy-chain mode). so as not to affect calibration, do not take measurement and keep the devices in sample mode (ecs = 0, sc2 = 0, smplb = 0). after power-up, if the devices do not calibrate regularly, a temperature offset drift of q 1.5 f v/c can occur. monitoring less than 12/16 cells the devices can monitor from 3 (v p > +6v) to 12/16 cells (v p < +65v). when monitoring less than the maxi - mum number of possible cells per device, connect the most negative cell stack voltage to the bottom of the voltage input string (cv0). the unused cv_ inputs at the top of the string should be shorted together and connected to v p . leave the unused ba_, ct_ , and cb_ pins unconnected. reading total cell stack voltage besides monitoring the individual cell voltages, the devices can monitor the total voltage of the cell stack. an internal resistive voltage-divider between v p and agnd divides the stack voltage by 12 (MAX14920) or 16 (max14921). this provides a way to quickly determine the state of the total battery pack, as well as the average voltage of all cells. the settling time of aout is 60 f s. to t samp l (ms) output error (mv) 9 8 7 6 5 4 3 2 0.1 1.0 10.0 100.0 0 11 0 v cn = 65 v v c = 4.5v c samp l = 1 f c par = 1pf output error vs. sampling time maxim integrated MAX14920/max14921 high-accuracy 12-/16-cell measurement afes http://www..net/ datasheet pdf - http://www..net/
18 figure 7. spi serial interface bits read out the total cell stack voltage, set the [ecs, sc0, sc1, sc2, sc3] bits to [0, 0, 0, 1, 1]. the total cell stack voltage can be read during the sample or hold phase. spi serial interface control of the devices is done through a 24-bit spi inter - face. the controller sends the serial data to the devices through the sdi input. the devices simultaneously send out monitoring data at the sdo output. this scheme allows daisy-chained operation with other daisy-chain - able devices, such as adc converters. figure 7 shows the serial bit sequence. cb1 is the first bit expected from the controller and c1 is the first bit that the devices sent to the controller. the sdo data changes on the falling edge of the sclk signals. the devices sample the sdi data on the rising edge of sclk. spi configuration/control bits the configuration/control bits allow enabling of the charge-balance switches, sampling and holding of all the cell voltages, selecting the cell for voltage output, selecting the t_ input channels, and enabling diagnos - tics mode. table 1 describes the bits that the devices receive from the host controller for configuration and control through sdi. table 1. spi configuration/control bits name bits access reset description cb1 0 w 0 0: set ba1 output low 1: set ba1 output high cb2 1 w 0 0: set ba2 output low 1: set ba2 output high cb3 2 w 0 0: set ba3 output low 1: set ba3 output high cb4 3 w 0 0: set ba4 output low 1: set ba4 output high cb5 4 w 0 0: set ba5 output low 1: set ba5 output high cb6 5 w 0 0: set ba6 output low 1: set ba6 output high cb7 6 w 0 0: set ba7 output low 1: set ba7 output high cb8 7 w 0 0: set ba8 output low 1: set ba8 output high sclk sdi sdo cb 1 smplb lopw cb 2c b3 cb 4c b5 cb 6c b7 cb 8c b9 cb 10 cb 11 cb 12 cb 13 cb 14 cb 15 cb 16 ecss c0 sc 1s c2 sc 3d ia gx x c1 uv _v ao t c2 c3 c4 c5 c6 c7 c8 c9 c1 0c 11 c1 2c 13 c1 4c 15 c1 6o p0 op 1r ev 0r ev 1u v_ vp rdy x cs maxim integrated MAX14920/max14921 high-accuracy 12-/16-cell measurement afes http://www..net/ datasheet pdf - http://www..net/
19 table 1. spi configuration/control bits (continued) * not available on the MAX14920. setting the bit to 0 or 1 does not affect the operating of the MAX14920. ** for the MAX14920, if n > 12, v aout = 0v. name bits access reset description cb9 8 r/w 0 0: set ba9 output low 1: set ba9 output high cb10 9 r/w 0 0: set ba10 output low 1: set ba10 output high cb11 10 r/w 0 0: set ba11 output low 1: set ba11 output high cb12* 11 r/w 0 0: set ba12 output low 1: set ba12 output high cb13* 12 r/w 0 0: set ba13 output low 1: set ba13 output high cb14* 13 r/w 0 0: set ba14 output low 1: set ba14 output high cb15* 14 r/w 0 0: set ba15 output low 1: set ba15 output high cb16* 15 r/w 0 0: set ba16 output low 1: set ba16 output high ecs 16 r/w 0 0: cell selection is disabled 1: cell selection is enabled sc0 17 r/w 0 [ecs, sc0, sc1, sc2, sc3] 1 C sc0, sc1, sc2, sc3: selects the cell for voltage readout during hold phase.** the selected cell voltage is routed to aout after the rising cs edge. see table 2. 0 C 0, 0, 0, 0: aout is three-stated and sampling switches are configured for parasitic capacitance error calibration. 0 C 1, 0, 0, 0: aout is three-statedand self-calibration of buffer amplifier offset voltage is initiated after the following rising cs . 0 C sc0, sc1, 0, 1: switches the t1, t2. t2 analog inputs directly to aout. see table 3. 0 C 0, 0, 1, 1: v p /12 (MAX14920) or v p /16 (max14921) voltage is routed to aout on the next rising cs 0 C sc0, sc1, 1, 1: routes and buffers the t1, t2. t3 to aout. see table 3. sc1 18 r/w 0 sc2 19 r/w 0 sc3 20 r/w 0 smplb 21 r/w 0 0: device in sample phase if sampl input is logic-high 1: device in hold phase diag 22 r/w 0 0: normal operation 1: diagnostic enable, 10 f a leakage is sunk on all cv_ inputs (cv0Ccv16). lopw 23 r/w 0 0: normal operation 1: low-power mode enabled. current into ldoin is reduced to 125 f a. current into v p is reduced to 1 f a. maxim integrated MAX14920/max14921 high-accuracy 12-/16-cell measurement afes http://www..net/ datasheet pdf - http://www..net/
20 table 2. cell selection table 3. analog input selection * for max14921 only. cell sc0 sc1 sc2 sc3 1 0 0 0 0 2 1 0 0 0 3 0 1 0 0 4 1 1 0 0 5 0 0 1 0 6 1 0 1 0 7 0 1 1 0 8 1 1 1 0 9 0 0 0 1 10 1 0 0 1 11 0 1 0 1 12 1 1 0 1 13* 0 0 1 1 14* 1 0 1 1 15* 0 1 1 1 16* 1 1 1 1 t_ sc0 sc1 t1 1 0 t2 0 1 t3 1 1 maxim integrated MAX14920/max14921 high-accuracy 12-/16-cell measurement afes http://www..net/ datasheet pdf - http://www..net/
21 spi monitoring bits the monitoring bits provide feedback of undervoltage conditions and thermal shutdown, as well as indication when the devices are ready for operation after power-up. table 4 describes the diagnostics/monitoring bits that the devices send back to the host controller through the sdo output. flexible logic interface the serial/parallel logic control interface logic levels can be defined to be in a range between +1.62v (min) and +5.5v (max). the voltage applied to the v l pin defines the logic levels. choose the v l voltage to match the con - troller and adcs i/o logic levels. table 4. spi monitoring bits * not available on the MAX14920. setting the bit to 0 or 1 does not affect the operating of the MAX14920. name bits access description c1 0 r 1: during hold phase if cell 1 voltage is below uv_v cvth or above v a c2 1 r 1: during hold phase if cell 2 voltage is below uv_v cvth or above v a c3 2 r 1: during hold phase if cell 3 voltage is below uv_v cvth or above v a c4 3 r 1: during hold phase if cell 4 voltage is below uv_v cvth or above v a c5 4 r 1: during hold phase if cell 5 voltage is below uv_v cvth or above v a c6 5 r 1: during hold phase if cell 6 voltage is below uv_v cvth or above v a c7 6 r 1: during hold phase if cell 7 voltage is below uv_v cvth or above v a c8 7 r 1: during hold phase if cell 8 voltage is below uv_v cvth or above v a c9 8 r 1: during hold phase if cell 9 voltage is below uv_v cvth or above v a c10 9 r 1: during hold phase if cell 10 voltage is below uv_v cvth or above v a c11 10 r 1: during hold phase if cell 11 voltage is below uv_v cvth or above v a c12* 11 r 1: during hold phase if cell 12 voltage is below uv_v cvth or above v a c13* 12 r 1: during hold phase if cell 13 voltage is below uv_v cvth or above v a c14* 13 r 1: during hold phase if cell 14 voltage is below uv_v cvth or above v a c15* 14 r 1: during hold phase if cell 15 voltage is below uv_v cvth or above v a c16* 15 r 1: during hold phase if cell 16 voltage is below uv_v cvth or above v a op0 16 r product identifying bits max14921 (op0 = 0, op1 = 0) MAX14920 (op0 = 1, op1 = 0) op1 17 r rev0 18 r die version MAX14920/max14921 version bits rev1 19 r uv_va 20 r 1: v a is below uv_v avth uv_vp 21 r 1: v p is below uv_v pvth. if lopw = 1, v p uvlo circuit is disabled and this bit is always set to 1 rdy 22 r 1: device is not ready to operate (power-up phase or buffer amplifier is in self-calibration procedure) ot 23 r 1: device is in thermal shutdown maxim integrated MAX14920/max14921 high-accuracy 12-/16-cell measurement afes http://www..net/ datasheet pdf - http://www..net/
22 linear regulator the internal linear regulator has ldoin as its input volt - age and regulates this down to +5v q 5% at the v a output with a load current of 10ma (max). the ldo is automati - cally enabled when ldoin is above +5.5v. the internal ldo is short-circuit protected with a current limit higher than 14ma (22ma, typ). an external +5v regulator can be used instead of the internal one. when using an external +5v regular, ldoin must be connected to v a . thermal protection the devices have thermal shutdown to protect them against thermal overheating. in thermal shutdown, the ldo, amplifier, and charge-balance circuitry stop opera - tion. the spi interface is functional in thermal shutdown. shutdown mode the devices can be placed into low standby-power shutdown mode through the lopw bit. the internal ldo remains on and the amplifier disabled, bringing the v p supply current down to 1 f a (max). analog/temperature inputs the t1, t2, and t3 inputs are single-ended, cv0- referenced, general-purpose analog inputs that are mul - tiplexed to aout or to aout through a buffer ( figure 8 ). these inputs can be used for connection of temperature sensors or for a current monitor. the total mux and switch series resistance is less than 200 i . in applications where the load current flowing to the aout output is so high that significant errors are introduced due to series resistance in the voltage source and/or the signal path, use the buffer amplifier to improve accuracy. route the t_ inputs through the buffer to aout by setting the spi bits [ecs, sc0, sc1, sc2, sc3] = [0, b, a, 1, 1]. route the t_ inputs directly to the aout output by setting the bits [ecs, sc0, sc1, sc2, sc3 = [0, b, a, 0, 1]. bits a and b select one of the three t_ inputs or three-state the aout output. three-stating the aout output the aout output can be three-stated to share this pin with other external signal sources, such as additional temperature sensors. use the ecs and sc_ bits to three- state the aout output. charge balancing low-voltage enhancement-mode n-channel fets can be connected for passive balancing of cells. select low on- resistance fets with a v t less than v bah . connect the fets between each cells anode and cathode through a current-limiting resistor in the drain ( figure 9 ). the charge-balancing fets can be enabled through spi control. an internal 600 i (typ)/900 i (max) pulldown resistor assures that the fet is normally switched off. when balancing is active, a leakage current of 5 f a is sunk from cv_. in addition, an internal balancing current flowing from cvn to cvn - 1 of 10ma (max) is present, where n = 1C12 (MAX14920) and n = 1C16 (max14921). the power dissipation created by the internal current during balancing should be considered for total package power management. diagnostics the devices in tegrated diagnostics allow detection of shorts between wires, as well as open-wire conditions of the cv_ pins. figure 8. analog / temperature measurement figure 9. charge balancing t1 t2 t3 buffer aout spi control *n = 1?12 (MAX14920) and n = 1?16 (max14921 ) cvn* - 1 cvn* celln* r bal ban* bal 600i MAX14920 max14921 maxim integrated MAX14920/max14921 high-accuracy 12-/16-cell measurement afes http://www..net/ datasheet pdf - http://www..net/
23 shorts between cell connections can be detected during normal operation. the cell readout voltage results in ~0v or ~v a depending on where the short happens. in the case of shorts, the maximum currents flowing in/out of the pins must be limited and overvoltages avoided, including the external components (balancing fets and sampling capacitors). open-wire conditions between the cv_ inputs and the cells can be detected in two different ways: the first method of open-wire detection: set the diag bit to 1 while in the sampling phase. this applies a leakage current of 10 f a to the cvn inputs. if cvn is unconnected, the leakage current starts discharg - ing the sampling capacitor with a slew rate of i leak / c samlpe (~10 f a /1 f f = 100mv/10ms) down to cvn - 1. two successive readouts show considerable cell voltage change in case of an open wire. alternatively, waiting for a sampling time of ~300ms to 500ms reduces the cell voltage to below the uv_vc vth threshold voltage. first open-wire detection procedure: ? set diag bit to 1 ? wait > 0.5s before hold phase ? read out the cn bit or the cvn voltage under spi control, where n = 1C12 (MAX14920) and n = 1C16 (max14921) the second method of open-wire detection: to check for a single open-wire connection, it is faster to enable the balancing fet only on the selected cell during the sampling phase and then reading out the selected cell voltage. if cvn is unconnected, the balancing fet rapidly (time depends on the balancing resistance used) shorts cvn to cvn - 1 and the readout phase shows ~0v or cvn and a voltage higher than v a on cvn + 1. second open-wire detection procedure: ? set the ban bit to 1 ? wait for a time of r bal x c sample before switching to the hold phase ? route the cvn voltage to aout ? repeat this procedure for all cells during this procedure, the capacitors and external fets need to withstand a voltage equal to v cvn - v cvn-1 , where n = 1C12 (MAX14920) and n = 1C16 (max14921). input-voltage clamping the devices have internal esd-protection diodes that can clamp input voltage lower than agnd or higher than v p (cvn where n is > 1) or 6 volts for (cv1) during a fault con - dition. connect series resistors (r lim ) to the inputs to limit the currents flowing through the forward-biased diodes during fault conditions ( figure 10 ). choose current-limiting resistors so the input currents are limited to i cv_ (max) = 10ma. the additional power dissipation due to the fault currents needs to be calculated when a voltage-clamping condition occurs on another channel that is not being measured. sampling capacitors and balancing fets must be chosen appropriately or protected with external voltage clamps to survive such events. power sequencing the v a and v l supplies can be applied at any sequence with respect to each other and also independently of the v p and supplies cv_ inputs. the v p voltage has to con - nect to the highest voltage of the cell stack. figure 10. input-voltage clamp ctn* c sample v p cvn* cvn*- 1 r lim r lim ban* r bal cbn* agnd cv0 *n = 1?12 (MAX14920) and n = 1?16 (max14921) ba1 cv1 MAX14920 max14921 maxim integrated MAX14920/max14921 high-accuracy 12-/16-cell measurement afes http://www..net/ datasheet pdf - http://www..net/
24 applications information sampling speed and capacitor- selection considerations capacitor values of 1 f f are recommended for achieving low errors and at high sampling rates, with sample and hold times in the order of 5ms. with 1 f f capacitors and good pcb layout, charge injection-error correction is normally not required. if higher/lower sampling speeds are required, the sam - pling capacitors and/or the series resistors at the cell connections can be reduced and/or increased. the cell sampling capacitors connected to the ct_ and cb_ terminals affect: ? speed of operation ? cell readout accuracy the smaller the sampling capacitor values, the lower their rc time constant and hence the faster their charg - ing time. therefore, for higher-speed operation, smaller capacitor values can be selected. one application case can be when the cell voltages are known to only vary by small amounts from one sample to the next. in this case, the sampling capacitors can be made smaller, as the sampling phases only need to charge the capacitors by the charge lost during the previous level shift and hold phase, including the small change in cell voltage. see the measurement accuracy section for details on how to calculate the voltage drop due to these two factors. for example, sampling capaci - tors of approximately 100nf can be adequate, thereby reducing the sampling phase by a factor of 10. if this technique is used, the initial sampling times, after initial power-up, either have to be made longer to allow the ini - tially discharged sampling capacitors to charge up to the cell voltages, or the initial samples are disregarded until the monitored voltages stabilize to their final cell value. the accuracy dependence on the capacitor values is determined by the discharge during the hold phase and by the errors introduced during level shifting (both were previously described). by speeding up the readout of the cell voltages during the hold phase, discharging is reduced. note that the last cell voltage being read out is most affected by discharging, due to its longer hold delay until being read out. smaller capacitor values are prone to higher charge injection errors caused by level shifting. both low-capacitance layout and level-shift com - pensation reduce these errors. typical application circuit figure 11 shows a high-accuracy measurement applica - tion based on an accurate 16-bit adc, together with a high-quality voltage reference. the internal linear regula - tor is used for supplying v a (+5v), and uses the sampl input for controlling the cell voltage sample and hold times. thermistors are connected to the t1, t2, and t3 inputs to monitor three temperatures. if less absolute measurement accuracy is acceptable, an adc with internal reference, such as the max11163, can be used. in applications where accuracy is not a critical factor, a microcontrollers internal adc may be adequate. multipack applications in applications that require more than 12/16 cells to achieve higher voltages, multiple cell packs can be stacked. each pack in the stack does not have to have the same number of cells. a minimum of +6v or 3 cells can be monitored by the devices. in stacked packs, the sample signal can either be cen - trally controlled by a common signal for simultaneous sampling, or the sample/hold can be initiated through spi. two cell packs stacked on one another can be interconnected through an spi or other communication interface. the packs can either have internal controllers or multiple packs can be controlled by one common con - troller. internal controllers perform autonomous calibra - tion and measurements, and allow an external controller to collect the data on demand. this scheme is shown in figure 12 . to translate the interpack communication sig - nals between the differing common-mode pack voltages, use opto-isolators, digital isolators, or digital ground level shifters ( figure 12 ). layout considerations keep the pcb traces to the sampling capacitors as short as possible and minimize parasitic capacitance between the capacitor pins and the ground plane. maxim integrated MAX14920/max14921 high-accuracy 12-/16-cell measurement afes http://www..net/ datasheet pdf - http://www..net/
25 figure 11. typical application circuit v a ba15 aout sampl sclk sdo sdi cv15 cv16 v p ldoin ba16 ba1 cv0 agnd cv14 cv1 ct16 1f cb16 ct15 1f cb15 ct14 1f 1f 1f max11163 16-bit adc external reference c power- supply unit max6126 cb14 t_ v a v l 1f ct1 cb2 1f ct2 cb3 1f ct3 MAX14920 max14921 cs en dgnd maxim integrated MAX14920/max14921 high-accuracy 12-/16-cell measurement afes http://www..net/ datasheet pdf - http://www..net/
26 figure 12. stacked battery pack application diagram based on daisy-chained spi MAX14920 max14921 max14850 max17501 adc controller sdi sdo v a sdi sdo cs clk comn gnd gnd spi1 comn-1 vccn-1 spi2 vccn v p MAX14920 max14921 max14850 max17501 adc controller sdi sdo v a com1 gnd gnd spi1 spi2 vcc1 v p controller gnd mosi cs clkm iso v cc maxim integrated MAX14920/max14921 high-accuracy 12-/16-cell measurement afes http://www..net/ datasheet pdf - http://www..net/
27 functional diagram v p ct9 cb9 ct10 cb10 ct11 cb11 ct12 cb12 ct13* cb13* ct14* cb14* ct15* cb15* ct16* cb16* agnd ct1 cb1 ct2 cb2 ct3 cb3 ct4 cb4 ct5 cb5 ct6 cb6 ct7 cb7 ct8 cb8 dgnd cv16* ba16* cv15* ba15* cv14* t1 t2 t3 ldoin v a aout en sampl cs sclk spi sdi sdo v l +5v ldo ba14* cv13* ba13* cv12 ba1 2 cv11 ba1 1 cv10 ba1 0 cv 9 ba9 cv 8 ba8 cv 7 ba7 cv 6 ba6 cv 5 ba5 cv 4 ba4 cv 3 ba3 cv 2 ba2 cv 1 ba1 cv 0 MAX14920 max14921 source select/ calibratio n *max14921 only . maxim integrated MAX14920/max14921 high-accuracy 12-/16-cell measurement afes http://www..net/ datasheet pdf - http://www..net/
28 ordering information package information for the latest package outline information and land patterns (foot - prints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. chip information process: bicmos part cells temp range pin- package MAX14920 ecb+ 12 -40 n c to +85 n c 64 tqfp-ep* max14921 ecs+ 16 -40 n c to +85 n c 80 tqfp package type package code outline no. land pattern no. 64 tqfp-ep c64e+10 21-0084 90-0329 80 tqfp c80+1 21-0072 maxim integrated MAX14920/max14921 high-accuracy 12-/16-cell measurement afes http://www..net/ datasheet pdf - http://www..net/
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 29 ? 2012 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. revision history revision number revision date description pages changed 0 10/12 initial release 1 2/13 removed future products asterisks from the MAX14920 28 MAX14920/max14921 high-accuracy 12-/16-cell measurement afes http://www..net/ datasheet pdf - http://www..net/

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